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Commit 07c523f1 authored by Jason Cooper's avatar Jason Cooper
Browse files

Merge branch 'irqchip/stacked-omap' into irqchip/core

parents 37b25fff 7136d457

Documentation/devicetree/bindings/arm/gic.txt

+0 −6
Original line number Diff line number Diff line
@@ -56,11 +56,6 @@ Optional 
  regions, used when the GIC doesn't have banked registers. The offset is

  cpu-offset * cpu-nr.



- arm,routable-irqs : Total number of gic irq inputs which are not directly

		  connected from the peripherals, but are routed dynamically

		  by a crossbar/multiplexer preceding the GIC. The GIC irq

		  input line is assigned dynamically when the corresponding

		  peripheral's crossbar line is mapped.

Example:



	intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example: 
		#interrupt-cells = <3>;

		#address-cells = <1>;

		interrupt-controller;

		arm,routable-irqs = <160>;

		reg = <0xfff11000 0x1000>,

		      <0xfff10100 0x100>;

	};

Documentation/devicetree/bindings/arm/omap/crossbar.txt

+5 −13
Original line number Diff line number Diff line
@@ -9,7 +9,9 @@ inputs. 
Required properties:

- compatible : Should be "ti,irq-crossbar"

- reg: Base address and the size of the crossbar registers.

- ti,max-irqs: Total number of irqs available at the interrupt controller.

- interrupt-controller: indicates that this block is an interrupt controller.

- interrupt-parent: the interrupt controller this block is connected to.

- ti,max-irqs: Total number of irqs available at the parent interrupt controller.

- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.

- ti,reg-size: Size of a individual register in bytes. Every individual

	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties: 
  when the interrupt controller irq is unused (when not provided, default is 0)



Examples:

		crossbar_mpu: @4a020000 {

		crossbar_mpu: crossbar@4a002a48 {

			compatible = "ti,irq-crossbar";

			reg = <0x4a002a48 0x130>;

			ti,max-irqs = <160>;

			ti,max-crossbar-sources = <400>;

			ti,reg-size = <2>;

			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;

			ti,irqs-reserved = <0 1 2 3 5 6 131 132>;

			ti,irqs-skip = <10 133 139 140>;

		};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details. 


An interrupt consumer on an SoC using crossbar will use:

	interrupts = <GIC_SPI request_number interrupt_level>

When the request number is between 0 to that described by

"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the

request_number is greater than "ti,max-crossbar-sources", then it is mapped as a

quirky hardware mapping direct to GIC.



Example:

	device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example: 
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

		...

	};
 


	device_y@0x4a033000 {

		/* Direct mapped GIC SPI 1 used */

		interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;

		...

	};

Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu

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+33 −0
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TI OMAP4 Wake-up Generator



All TI OMAP4/5 (and their derivatives) an interrupt controller that

routes interrupts to the GIC, and also serves as a wakeup source. It

is also referred to as "WUGEN-MPU", hence the name of the binding.



Reguired properties:



- compatible : should contain at least "ti,omap4-wugen-mpu" or

  "ti,omap5-wugen-mpu"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value must be 3.

- interrupt-parent : a phandle to the GIC these interrupts are routed

  to.



Notes:



- Because this HW ultimately routes interrupts to the GIC, the

  interrupt specifier must be that of the GIC.

- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs

  are explicitly forbiden.



Example:



       wakeupgen: interrupt-controller@48281000 {

               compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";

               interrupt-controller;

               #interrupt-cells = <3>;

               reg = <0x48281000 0x1000>;

               interrupt-parent = <&gic>;

       };

arch/arm/boot/dts/am4372.dtsi

+10 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 


/ {

	compatible = "ti,am4372", "ti,am43";

	interrupt-parent = <&gic>;

	interrupt-parent = <&wakeupgen>;





	aliases {
@@ -48,6 +48,15 @@ 
		#interrupt-cells = <3>;

		reg = <0x48241000 0x1000>,

		      <0x48240100 0x0100>;

		interrupt-parent = <&gic>;

	};



	wakeupgen: interrupt-controller@48281000 {

		compatible = "ti,omap4-wugen-mpu";

		interrupt-controller;

		#interrupt-cells = <3>;

		reg = <0x48281000 0x1000>;

		interrupt-parent = <&gic>;

	};



	l2-cache-controller@48242000 {

arch/arm/boot/dts/am437x-gp-evm.dts

+0 −1
Original line number Diff line number Diff line
@@ -352,7 +352,6 @@ 
		reg = <0x24>;

		compatible = "ti,tps65218";

		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */

		interrupt-parent = <&gic>;

		interrupt-controller;

		#interrupt-cells = <2>;