Commit 06f2d879 authored Feb 08, 2017 by Easwar Hariharan Committed by Greg Kroah-Hartman Oct 21, 2017

IB/hfi1: Use static CTLE with Preset 6 for integrated HFIs




[ Upstream commit 39e2afa8d042a53d855137d4c5a689a6f5492b39 ]

After extended testing, it was found that the previous PCIe Gen
3 recipe, which used adaptive CTLE with Preset 4, could cause an
NMI/Surprise Link Down in about 1 in 100 to 1 in 1000 power cycles on
some platforms. New EV data combined with extensive empirical data
indicates that the new recipe should use static CTLE with Preset 6 for
all integrated silicon SKUs.

Fixes: c3f8de0b ("IB/hfi1: Add static PCIe Gen3 CTLE tuning")
Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Easwar Hariharan <easwar.hariharan@intel.com>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 939f4f6e

drivers/infiniband/hw/hfi1/pcie.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -673,12 +673,12 @@ MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested

		#define UNSET_PSET 255
		#define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */
		#define DEFAULT_MCP_PSET 4 /* MCP HFI */
		#define DEFAULT_MCP_PSET 6 /* MCP HFI */
		static uint pcie_pset = UNSET_PSET;
		module_param(pcie_pset, uint, S_IRUGO);
		MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");

		static uint pcie_ctle = 1; /* discrete on, integrated off */
		static uint pcie_ctle = 3; /* discrete on, integrated on */
		module_param(pcie_ctle, uint, S_IRUGO);
		MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off");