drm/msm/dp: fix DP configuration programming



Fix the DP controller programming as per hardware recommendations
to avoid link issues.

CRs-Fixed: 2117770
Change-Id: I39cfaf0d8f21c93e57d547cd8b3110c978fb8e07
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>

parent d0c491f1

drivers/gpu/drm/msm/dp/dp_catalog.c

+0 −2

Original line number	Diff line number	Diff line
		@@ -550,8 +550,6 @@ static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u32 cfg)
		pr_debug("DP_CONFIGURATION_CTRL=0x%x\n", cfg);

		dp_write(base + DP_CONFIGURATION_CTRL, cfg);
		dp_write(base + DP_MAINLINK_LEVELS, 0xa08);
		dp_write(base + MMSS_DP_ASYNC_FIFO_CONFIG, 0x1);
		}

		static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl)