Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 064e297c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (30 commits)
  Blackfin: SMP: fix continuation lines
  Blackfin: acvilon: fix timeout usage for I2C
  Blackfin: fix typo in BF537 IRQ comment
  Blackfin: unify duplicate MEM_MT48LC32M8A2_75 kconfig options
  Blackfin: set ARCH_KMALLOC_MINALIGN
  Blackfin: use atomic kmalloc in L1 alloc so it too can be atomic
  Blackfin: another year of changes (update copyright in boot log)
  Blackfin: optimize strncpy a bit
  Blackfin: isram: clean up ITEST_COMMAND macro and improve the selftests
  Blackfin: move string functions to normal lib/ assembly
  Blackfin: SIC: cut down on IAR MMR reads a bit
  Blackfin: bf537-minotaur: fix build errors due to header changes
  Blackfin: kgdb: pass up the CC register instead of a 0 stub
  Blackfin: handle HW errors in the new "FAULT" printing code
  Blackfin: show the whole accumulator in the pseudo DBG insn
  Blackfin: support all possible registers in the pseudo instructions
  Blackfin: add support for the DBG (debug output) pseudo insn
  Blackfin: change the BUG opcode to an unused 16-bit opcode
  Blackfin: allow NMI watchdog to be used w/RETN as a scratch reg
  Blackfin: add support for the DBGA (debug assert) pseudo insn
  ...
parents f1377118 db52ecc2

arch/blackfin/Kconfig

+29 −32
Original line number Diff line number Diff line
@@ -348,7 +348,7 @@ config MEM_MT48LC16M16A2TG_75 


config MEM_MT48LC32M8A2_75

	bool

	depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)

	depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)

	default y



config MEM_MT48LC8M32B2B5_7
@@ -361,11 +361,6 @@ config MEM_MT48LC32M16A2TG_75 
	depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)

	default y



config MEM_MT48LC32M8A2_75

	bool

	depends on (BFIN518F_EZBRD)

	default y



config MEM_MT48H32M16LFCJ_75

	bool

	depends on (BFIN526_EZBRD)
@@ -791,6 +786,34 @@ config MEMCPY_L1 
	  If enabled, the memcpy function is linked

	  into L1 instruction memory. (less latency)



config STRCMP_L1

	bool "locate strcmp function in L1 Memory"

	default y

	help

	  If enabled, the strcmp function is linked

	  into L1 instruction memory (less latency).



config STRNCMP_L1

	bool "locate strncmp function in L1 Memory"

	default y

	help

	  If enabled, the strncmp function is linked

	  into L1 instruction memory (less latency).



config STRCPY_L1

	bool "locate strcpy function in L1 Memory"

	default y

	help

	  If enabled, the strcpy function is linked

	  into L1 instruction memory (less latency).



config STRNCPY_L1

	bool "locate strncpy function in L1 Memory"

	default y

	help

	  If enabled, the strncpy function is linked

	  into L1 instruction memory (less latency).



config SYS_BFIN_SPINLOCK_L1

	bool "Locate sys_bfin_spinlock function in L1 Memory"

	default y
@@ -1187,32 +1210,6 @@ config PM_BFIN_SLEEP 
	  If unsure, select "Sleep Deeper".

endchoice



config PM_WAKEUP_BY_GPIO

	bool "Allow Wakeup from Standby by GPIO"

	depends on PM && !BF54x



config PM_WAKEUP_GPIO_NUMBER

	int "GPIO number"

	range 0 47

	depends on PM_WAKEUP_BY_GPIO

	default 2



choice

	prompt "GPIO Polarity"

	depends on PM_WAKEUP_BY_GPIO

	default PM_WAKEUP_GPIO_POLAR_H

config  PM_WAKEUP_GPIO_POLAR_H

	bool "Active High"

config  PM_WAKEUP_GPIO_POLAR_L

	bool "Active Low"

config  PM_WAKEUP_GPIO_POLAR_EDGE_F

	bool "Falling EDGE"

config  PM_WAKEUP_GPIO_POLAR_EDGE_R

	bool "Rising EDGE"

config  PM_WAKEUP_GPIO_POLAR_EDGE_B

	bool "Both EDGE"

endchoice



comment "Possible Suspend Mem / Hibernate Wake-Up Sources"

	depends on PM

arch/blackfin/Kconfig.debug

+10 −1
Original line number Diff line number Diff line
@@ -238,7 +238,7 @@ config EARLY_PRINTK 
config NMI_WATCHDOG

	bool "Enable NMI watchdog to help debugging lockup on SMP"

	default n

	depends on (SMP && !BFIN_SCRATCH_REG_RETN)

	depends on SMP

	help

	  If any CPU in the system does not execute the period local timer

	  interrupt for more than 5 seconds, then the NMI handler dumps debug
@@ -264,4 +264,13 @@ config BFIN_ISRAM_SELF_TEST 
	help

	  Run some self tests of the isram driver code at boot.



config BFIN_PSEUDODBG_INSNS

	bool "Support pseudo debug instructions"

	default n

	help

	  This option allows the kernel to emulate some pseudo instructions which

	  allow simulator test cases to be run under Linux with no changes.



	  Most people should say N here.



endmenu

arch/blackfin/include/asm/bfin-global.h

+6 −0
Original line number Diff line number Diff line
@@ -39,9 +39,15 @@ extern unsigned long sclk_to_usecs(unsigned long sclk); 
extern unsigned long usecs_to_sclk(unsigned long usecs);



struct pt_regs;

#if defined(CONFIG_DEBUG_VERBOSE)

extern void dump_bfin_process(struct pt_regs *regs);

extern void dump_bfin_mem(struct pt_regs *regs);

extern void dump_bfin_trace_buffer(void);

#else

#define dump_bfin_process(regs)

#define dump_bfin_mem(regs)

#define dump_bfin_trace_buffer()

#endif



/* init functions only */

extern int init_arch_irq(void);

arch/blackfin/include/asm/bug.h

+6 −1
Original line number Diff line number Diff line
@@ -9,7 +9,12 @@ 


#ifdef CONFIG_BUG



#define BFIN_BUG_OPCODE	0xefcd

/*

 * This can be any undefined 16-bit opcode, meaning

 * ((opcode & 0xc000) != 0xc000)

 * Anything from 0x0001 to 0x000A (inclusive) will work

 */

#define BFIN_BUG_OPCODE	0x0001



#ifdef CONFIG_DEBUG_BUGVERBOSE

arch/blackfin/include/asm/cache.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)

#define SMP_CACHE_BYTES	L1_CACHE_BYTES



#define ARCH_KMALLOC_MINALIGN	L1_CACHE_BYTES



#ifdef CONFIG_SMP

#define __cacheline_aligned

#else