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Commit 05ad9c3e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-dt-for-v4.7' of... 

Merge tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Updates for v4.7" from Simon Horman:

* Configure NMI key as wakeup source in DT of kzm9g board
* Add SDHI support to DT of gose board
* Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC
* Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs
* Add IIC support to DT of r8a7794 SoC
* Add CAN support to DT of r8a7793 and r8a7794 SoCs
* Add SCIF2 support to r8a7790 device tree
* Use CAN, JPU and USB3.0 fallback compatibility string
  in DT of r8a7791 and r8a7790 SoCs

* tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
  ARM: dts: gose: Enable SDHI controllers
  ARM: dts: r8a7793: Add SDHI controllers
  ARM: dts: r8a7790: fix max-frequency for SDHI
  ARM: dts: kzm9g: Configure NMI key as wake-up source
  ARM: dts: r8a7790: lager: Enable UHS-I SDR-50
  ARM: dts: r8a7790: Set maximum frequencies for SDHI clocks
  ARM: dts: r8a7791: Use USB3.0 fallback compatibility string
  ARM: dts: r8a7790: Use USB3.0 fallback compatibility string
  ARM: dts: r8a7779: Correct interrupt type for ARM TWD
  ARM: dts: sh73a0: Correct interrupt type for ARM TWD
  ARM: dts: r8a7794: Add IIC nodes
  ARM: dts: r8a7794: add IIC clocks
  ARM: dts: r8a7793: add CAN nodes to device tree
  ARM: dts: r8a7793: add CAN clocks to device tree
  ARM: dts: r8a7794: add CAN nodes to device tree
  ARM: dts: r8a7794: add CAN clocks to device tree
  ARM: dts: r8a7790: use fallback can compatibility string
  ARM: dts: r8a7791: use fallback can compatibility string
  ARM: dts: r8a7790: Add SCIF2 device node
  ARM: dts: r8a7790: Add SCIF2 clock
  ...
parents 9b61aefc 6f92cb2f

arch/arm/boot/dts/r8a7779.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ 
		compatible = "arm,cortex-a9-twd-timer";

		reg = <0xf0000600 0x20>;

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;

		clocks = <&cpg_clocks R8A7779_CLK_ZS>;

	};

arch/arm/boot/dts/r8a7790-lager.dts

+20 −2
Original line number Diff line number Diff line
@@ -345,11 +345,25 @@ 
	sdhi0_pins: sd0 {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <3300>;

	};



	sdhi0_pins_uhs: sd0_uhs {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <1800>;

	};



	sdhi2_pins: sd2 {

		groups = "sdhi2_data4", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <3300>;

	};



	sdhi2_pins_uhs: sd2_uhs {

		groups = "sdhi2_data4", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <1800>;

	};



	mmc1_pins: mmc1 {
@@ -538,21 +552,25 @@ 


&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-names = "default";

	pinctrl-1 = <&sdhi0_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi0>;

	vqmmc-supply = <&vccq_sdhi0>;

	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;

	sd-uhs-sdr50;

	status = "okay";

};



&sdhi2 {

	pinctrl-0 = <&sdhi2_pins>;

	pinctrl-names = "default";

	pinctrl-1 = <&sdhi2_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi2>;

	vqmmc-supply = <&vccq_sdhi2>;

	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;

	sd-uhs-sdr50;

	status = "okay";

};

arch/arm/boot/dts/r8a7790.dtsi

+25 −7
Original line number Diff line number Diff line
@@ -589,6 +589,7 @@ 
		clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;

		dmas = <&dmac1 0xcd>, <&dmac1 0xce>;

		dma-names = "tx", "rx";

		max-frequency = <195000000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -600,6 +601,7 @@ 
		clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;

		dmas = <&dmac1 0xc9>, <&dmac1 0xca>;

		dma-names = "tx", "rx";

		max-frequency = <195000000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -611,6 +613,7 @@ 
		clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;

		dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;

		dma-names = "tx", "rx";

		max-frequency = <97500000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -622,6 +625,7 @@ 
		clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;

		dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;

		dma-names = "tx", "rx";

		max-frequency = <97500000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -732,6 +736,20 @@ 
		status = "disabled";

	};



	scif2: serial@e6e56000 {

		compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",

			     "renesas,scif";

		reg = <0 0xe6e56000 0 64>;

		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,

			 <&scif_clk>;

		clock-names = "fck", "brg_int", "scif_clk";

		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;

		dma-names = "tx", "rx";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



	hscif0: serial@e62c0000 {

		compatible = "renesas,hscif-r8a7790",

			     "renesas,rcar-gen2-hscif", "renesas,hscif";
@@ -968,7 +986,7 @@ 
	};



	can0: can@e6e80000 {

		compatible = "renesas,can-r8a7790";

		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";

		reg = <0 0xe6e80000 0 0x1000>;

		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
@@ -979,7 +997,7 @@ 
	};



	can1: can@e6e88000 {

		compatible = "renesas,can-r8a7790";

		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";

		reg = <0 0xe6e88000 0 0x1000>;

		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
@@ -990,7 +1008,7 @@ 
	};



	jpu: jpeg-codec@fe980000 {

		compatible = "renesas,jpu-r8a7790";

		compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";

		reg = <0 0xfe980000 0 0x10300>;

		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp1_clks R8A7790_CLK_JPU>;
@@ -1302,19 +1320,19 @@ 
		mstp3_clks: mstp3_clks@e615013c {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;

			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,

			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,

				 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,

				 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,

				 <&hp_clk>, <&hp_clk>;

			#clock-cells = <1>;

			clock-indices = <

				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3

				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3

				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0

				R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1

				R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1

			>;

			clock-output-names =

				"iic2", "tpu0", "mmcif1", "sdhi3",

				"iic2", "tpu0", "mmcif1", "scif2", "sdhi3",

				"sdhi2", "sdhi1", "sdhi0", "mmcif0",

				"iic0", "pciec", "iic1", "ssusb", "cmt1",

				"usbdmac0", "usbdmac1";
@@ -1499,7 +1517,7 @@ 
	};



	xhci: usb@ee000000 {

		compatible = "renesas,xhci-r8a7790";

		compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";

		reg = <0 0xee000000 0 0xc00>;

		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;

arch/arm/boot/dts/r8a7791.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -1013,7 +1013,7 @@ 
	};



	can0: can@e6e80000 {

		compatible = "renesas,can-r8a7791";

		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";

		reg = <0 0xe6e80000 0 0x1000>;

		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
@@ -1024,7 +1024,7 @@ 
	};



	can1: can@e6e88000 {

		compatible = "renesas,can-r8a7791";

		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";

		reg = <0 0xe6e88000 0 0x1000>;

		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
@@ -1035,7 +1035,7 @@ 
	};



	jpu: jpeg-codec@fe980000 {

		compatible = "renesas,jpu-r8a7791";

		compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";

		reg = <0 0xfe980000 0 0x10300>;

		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp1_clks R8A7791_CLK_JPU>;
@@ -1520,7 +1520,7 @@ 
	};



	xhci: usb@ee000000 {

		compatible = "renesas,xhci-r8a7791";

		compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";

		reg = <0 0xee000000 0 0xc00>;

		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;

arch/arm/boot/dts/r8a7793-gose.dts

+119 −0
Original line number Diff line number Diff line
@@ -158,6 +158,78 @@ 
		};

	};



	vcc_sdhi0: regulator@0 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI0 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi0: regulator@1 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI0 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};



	vcc_sdhi1: regulator@2 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI1 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi1: regulator@3 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI1 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};



	vcc_sdhi2: regulator@4 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI2 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vccq_sdhi2: regulator@5 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI2 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};



	audio_clock: audio_clock {

		compatible = "fixed-clock";

		#clock-cells = <0>;
@@ -273,6 +345,21 @@ 
		function = "intc";

	};



	sdhi0_pins: sd0 {

		renesas,groups = "sdhi0_data4", "sdhi0_ctrl";

		renesas,function = "sdhi0";

	};



	sdhi1_pins: sd1 {

		renesas,groups = "sdhi1_data4", "sdhi1_ctrl";

		renesas,function = "sdhi1";

	};



	sdhi2_pins: sd2 {

		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";

		renesas,function = "sdhi2";

	};



	qspi_pins: spi0 {

		groups = "qspi_ctrl", "qspi_data4";

		function = "qspi";
@@ -328,6 +415,38 @@ 
	status = "okay";

};



&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-names = "default";



	vmmc-supply = <&vcc_sdhi0>;

	vqmmc-supply = <&vccq_sdhi0>;

	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;

	status = "okay";

};



&sdhi1 {

	pinctrl-0 = <&sdhi1_pins>;

	pinctrl-names = "default";



	vmmc-supply = <&vcc_sdhi1>;

	vqmmc-supply = <&vccq_sdhi1>;

	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;

	status = "okay";

};



&sdhi2 {

	pinctrl-0 = <&sdhi2_pins>;

	pinctrl-names = "default";



	vmmc-supply = <&vcc_sdhi2>;

	vqmmc-supply = <&vccq_sdhi2>;

	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;

	status = "okay";

};



&qspi {

	pinctrl-0 = <&qspi_pins>;

	pinctrl-names = "default";