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Commit 054b93e4 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nv40: implement ctxprog/state generation 



The context programs are *very* simple compared to the ones used by
the binary driver.  There's notes in nv40_grctx.c explaining most of
the things we don't implement.  If we discover if/why any of it is
required further down the track, we'll handle it then.

The PGRAPH state generated for each chipset should match what NVIDIA
do almost exactly (there's a couple of exceptions).  If someone has
a lot of time on their hands, they could figure out the mapping of
object/method to PGRAPH register and demagic the initial state a little,
it's not terribly important however.

At time of commit, confirmed to be working at least well enough for
accelerated X (and where tested, for 3D apps) on NV40, NV43, NV44, NV46,
NV49, NV4A, NV4B and NV4E.

A module option has been added to force the use of external firmware
blobs if it becomes required.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 15bee69e

drivers/gpu/drm/nouveau/Makefile

+3 −2
Original line number Diff line number Diff line
@@ -9,13 +9,14 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ 
             nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \

             nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \

             nouveau_display.o nouveau_connector.o nouveau_fbcon.o \

	     nouveau_dp.o \

             nouveau_dp.o nouveau_grctx.o \

             nv04_timer.o \

             nv04_mc.o nv40_mc.o nv50_mc.o \

             nv04_fb.o nv10_fb.o nv40_fb.o \

             nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \

             nv04_graph.o nv10_graph.o nv20_graph.o \

             nv40_graph.o nv50_graph.o \

             nv40_grctx.o \

             nv04_instmem.o nv50_instmem.o \

             nv50_crtc.o nv50_dac.o nv50_sor.o \

             nv50_cursor.o nv50_display.o nv50_fbcon.o \

drivers/gpu/drm/nouveau/nouveau_drv.c

+4 −0
Original line number Diff line number Diff line
@@ -35,6 +35,10 @@ 


#include "drm_pciids.h"



MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");

int nouveau_ctxfw = 0;

module_param_named(ctxfw, nouveau_ctxfw, int, 0400);



MODULE_PARM_DESC(noagp, "Disable AGP");

int nouveau_noagp;

module_param_named(noagp, nouveau_noagp, int, 0400);

drivers/gpu/drm/nouveau/nouveau_drv.h

+10 −3
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ struct nouveau_fpriv { 
#include "nouveau_drm.h"

#include "nouveau_reg.h"

#include "nouveau_bios.h"

struct nouveau_grctx;



#define MAX_NUM_DCB_ENTRIES 16
@@ -317,6 +318,7 @@ struct nouveau_pgraph_engine { 
	bool accel_blocked;

	void *ctxprog;

	void *ctxvals;

	int grctx_size;



	int  (*init)(struct drm_device *);

	void (*takedown)(struct drm_device *);
@@ -647,6 +649,7 @@ extern int nouveau_fbpercrtc; 
extern char *nouveau_tv_norm;

extern int nouveau_reg_debug;

extern char *nouveau_vbios;

extern int nouveau_ctxfw;



/* nouveau_state.c */

extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
@@ -959,9 +962,7 @@ extern int nv40_graph_create_context(struct nouveau_channel *); 
extern void nv40_graph_destroy_context(struct nouveau_channel *);

extern int  nv40_graph_load_context(struct nouveau_channel *);

extern int  nv40_graph_unload_context(struct drm_device *);

extern int  nv40_grctx_init(struct drm_device *);

extern void nv40_grctx_fini(struct drm_device *);

extern void nv40_grctx_vals_load(struct drm_device *, struct nouveau_gpuobj *);

extern void nv40_grctx_init(struct nouveau_grctx *);



/* nv50_graph.c */

extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
@@ -975,6 +976,12 @@ extern int nv50_graph_load_context(struct nouveau_channel *); 
extern int  nv50_graph_unload_context(struct drm_device *);

extern void nv50_graph_context_switch(struct drm_device *);



/* nouveau_grctx.c */

extern int  nouveau_grctx_prog_load(struct drm_device *);

extern void nouveau_grctx_vals_load(struct drm_device *,

				    struct nouveau_gpuobj *);

extern void nouveau_grctx_fini(struct drm_device *);



/* nv04_instmem.c */

extern int  nv04_instmem_init(struct drm_device *);

extern void nv04_instmem_takedown(struct drm_device *);

drivers/gpu/drm/nouveau/nouveau_grctx.c

0 → 100644
+158 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2009 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */



#include <linux/firmware.h>



#include "drmP.h"

#include "nouveau_drv.h"



struct nouveau_ctxprog {

	uint32_t signature;

	uint8_t  version;

	uint16_t length;

	uint32_t data[];

} __attribute__ ((packed));



struct nouveau_ctxvals {

	uint32_t signature;

	uint8_t  version;

	uint32_t length;

	struct {

		uint32_t offset;

		uint32_t value;

	} data[];

} __attribute__ ((packed));



int

nouveau_grctx_prog_load(struct drm_device *dev)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;

	const int chipset = dev_priv->chipset;

	const struct firmware *fw;

	const struct nouveau_ctxprog *cp;

	const struct nouveau_ctxvals *cv;

	char name[32];

	int ret, i;



	if (!pgraph->ctxprog) {

		sprintf(name, "nouveau/nv%02x.ctxprog", chipset);

		ret = request_firmware(&fw, name, &dev->pdev->dev);

		if (ret) {

			NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);

			return ret;

		}



		pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL);

		if (!pgraph->ctxprog) {

			NV_ERROR(dev, "OOM copying ctxprog\n");

			release_firmware(fw);

			return -ENOMEM;

		}

		memcpy(pgraph->ctxprog, fw->data, fw->size);



		cp = pgraph->ctxprog;

		if (le32_to_cpu(cp->signature) != 0x5043564e ||

		    cp->version != 0 ||

		    le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {

			NV_ERROR(dev, "ctxprog invalid\n");

			release_firmware(fw);

			nouveau_grctx_fini(dev);

			return -EINVAL;

		}

		release_firmware(fw);

	}



	if (!pgraph->ctxvals) {

		sprintf(name, "nouveau/nv%02x.ctxvals", chipset);

		ret = request_firmware(&fw, name, &dev->pdev->dev);

		if (ret) {

			NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);

			nouveau_grctx_fini(dev);

			return ret;

		}



		pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);

		if (!pgraph->ctxprog) {

			NV_ERROR(dev, "OOM copying ctxprog\n");

			release_firmware(fw);

			nouveau_grctx_fini(dev);

			return -ENOMEM;

		}

		memcpy(pgraph->ctxvals, fw->data, fw->size);



		cv = (void *)pgraph->ctxvals;

		if (le32_to_cpu(cv->signature) != 0x5643564e ||

		    cv->version != 0 ||

		    le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {

			NV_ERROR(dev, "ctxvals invalid\n");

			release_firmware(fw);

			nouveau_grctx_fini(dev);

			return -EINVAL;

		}

		release_firmware(fw);

	}



	cp = pgraph->ctxprog;



	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);

	for (i = 0; i < le16_to_cpu(cp->length); i++)

		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,

			le32_to_cpu(cp->data[i]));



	return 0;

}



void

nouveau_grctx_fini(struct drm_device *dev)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;



	if (pgraph->ctxprog) {

		kfree(pgraph->ctxprog);

		pgraph->ctxprog = NULL;

	}



	if (pgraph->ctxvals) {

		kfree(pgraph->ctxprog);

		pgraph->ctxvals = NULL;

	}

}



void

nouveau_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;

	struct nouveau_ctxvals *cv = pgraph->ctxvals;

	int i;



	if (!cv)

		return;



	for (i = 0; i < le32_to_cpu(cv->length); i++)

		nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),

			le32_to_cpu(cv->data[i].value));

}

drivers/gpu/drm/nouveau/nouveau_grctx.h

0 → 100644
+133 −0
Original line number Diff line number Diff line 
#ifndef __NOUVEAU_GRCTX_H__

#define __NOUVEAU_GRCTX_H__



struct nouveau_grctx {

	struct drm_device *dev;



	enum {

		NOUVEAU_GRCTX_PROG,

		NOUVEAU_GRCTX_VALS

	} mode;

	void *data;



	uint32_t ctxprog_max;

	uint32_t ctxprog_len;

	uint32_t ctxprog_reg;

	int      ctxprog_label[32];

	uint32_t ctxvals_pos;

	uint32_t ctxvals_base;

};



#ifdef CP_CTX

static inline void

cp_out(struct nouveau_grctx *ctx, uint32_t inst)

{

	uint32_t *ctxprog = ctx->data;



	if (ctx->mode != NOUVEAU_GRCTX_PROG)

		return;



	BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);

	ctxprog[ctx->ctxprog_len++] = inst;

}



static inline void

cp_lsr(struct nouveau_grctx *ctx, uint32_t val)

{

	cp_out(ctx, CP_LOAD_SR | val);

}



static inline void

cp_ctx(struct nouveau_grctx *ctx, uint32_t reg, uint32_t length)

{

	ctx->ctxprog_reg = (reg - 0x00400000) >> 2;



	ctx->ctxvals_base = ctx->ctxvals_pos;

	ctx->ctxvals_pos = ctx->ctxvals_base + length;



	if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {

		cp_lsr(ctx, length);

		length = 0;

	}



	cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);

}



static inline void

cp_name(struct nouveau_grctx *ctx, int name)

{

	uint32_t *ctxprog = ctx->data;

	int i;



	if (ctx->mode != NOUVEAU_GRCTX_PROG)

		return;



	ctx->ctxprog_label[name] = ctx->ctxprog_len;

	for (i = 0; i < ctx->ctxprog_len; i++) {

		if ((ctxprog[i] & 0xfff00000) != 0xff400000)

			continue;

		if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))

			continue;

		ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |

			     (ctx->ctxprog_len << CP_BRA_IP_SHIFT);

	}

}



static inline void

_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)

{

	int ip = 0;



	if (mod != 2) {

		ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;

		if (ip == 0)

			ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);

	}



	cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |

		    (state ? 0 : CP_BRA_IF_CLEAR));

}

#define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)

#ifdef CP_BRA_MOD

#define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)

#define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)

#endif



static inline void

_cp_wait(struct nouveau_grctx *ctx, int flag, int state)

{

	cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));

}

#define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)



static inline void

_cp_set(struct nouveau_grctx *ctx, int flag, int state)

{

	cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));

}

#define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)



static inline void

cp_pos(struct nouveau_grctx *ctx, int offset)

{

	ctx->ctxvals_pos = offset;

	ctx->ctxvals_base = ctx->ctxvals_pos;



	cp_lsr(ctx, ctx->ctxvals_pos);

	cp_out(ctx, CP_SET_CONTEXT_POINTER);

}



static inline void

gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val)

{

	if (ctx->mode != NOUVEAU_GRCTX_VALS)

		return;



	reg = (reg - 0x00400000) / 4;

	reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;



	nv_wo32(ctx->dev, ctx->data, reg, val);

}

#endif



#endif