Commit 04d83f94 authored Feb 03, 2016 by Markos Chandras Committed by Ralf Baechle May 13, 2016

MIPS: traps: Make sure secondary cores have a sane ebase register

We shouldn't trust that the secondary cores will have a sane ebase register
(either from the bootloader or during the hardware design phase) so use the
ebase address as calculated by the boot CPU.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Petri Gynther <pgynther@google.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12328/

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent f270d881

arch/mips/kernel/traps.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -2116,6 +2116,13 @@ void per_cpu_trap_init(bool is_boot_cpu)
		* o read IntCtl.IPFDC to determine the fast debug channel interrupt
		*/
		if (cpu_has_mips_r2_r6) {
		/*
		* We shouldn't trust a secondary core has a sane EBASE register
		* so use the one calculated by the boot CPU.
		*/
		if (!is_boot_cpu)
		write_c0_ebase(ebase);

		cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
		cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
		cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;