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Commit 04aa2a7a authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Ajay Singh Parmar
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drm/msm/dp: add support for DisplayPort TPG for pixel data 



Add change to support test pattern generation for pixel data using
DP BIST pattern. Add a debugfs node to enable/disable TPG runtime
for debug purposes.

Change-Id: Idf62bf7636a1e678bbec5068ed7f60112a8ac458
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent 4af597e1

drivers/gpu/drm/msm/dp/dp_catalog.c

+51 −0
Original line number Diff line number Diff line
@@ -759,7 +759,57 @@ static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip) 
	dp_write(base + USB3_DP_COM_RESET_OVRD_CTRL, 0x00);

	/* make sure phy is brought out of reset */

	wmb();

}



static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,

	bool enable)

{

	struct dp_catalog_private *catalog;

	void __iomem *base;



	if (!panel) {

		pr_err("invalid input\n");

		return;

	}



	dp_catalog_get_priv(panel);

	base = catalog->io->dp_p0.base;



	if (!enable) {

		dp_write(base + MMSS_DP_TPG_MAIN_CONTROL, 0x0);

		dp_write(base + MMSS_DP_BIST_ENABLE, 0x0);

		dp_write(base + MMSS_DP_TIMING_ENGINE_EN, 0x0);

		wmb(); /* ensure Timing generator is turned off */

		return;

	}



	dp_write(base + MMSS_DP_INTF_CONFIG, 0x0);

	dp_write(base + MMSS_DP_INTF_HSYNC_CTL, panel->hsync_ctl);

	dp_write(base + MMSS_DP_INTF_VSYNC_PERIOD_F0, panel->vsync_period *

			panel->hsync_period);

	dp_write(base + MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, panel->v_sync_width *

			panel->hsync_period);

	dp_write(base + MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);

	dp_write(base + MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);

	dp_write(base + MMSS_DP_INTF_DISPLAY_HCTL, panel->display_hctl);

	dp_write(base + MMSS_DP_INTF_ACTIVE_HCTL, 0);

	dp_write(base + MMSS_INTF_DISPLAY_V_START_F0, panel->display_v_start);

	dp_write(base + MMSS_DP_INTF_DISPLAY_V_END_F0, panel->display_v_end);

	dp_write(base + MMSS_INTF_DISPLAY_V_START_F1, 0);

	dp_write(base + MMSS_DP_INTF_DISPLAY_V_END_F1, 0);

	dp_write(base + MMSS_DP_INTF_ACTIVE_V_START_F0, 0);

	dp_write(base + MMSS_DP_INTF_ACTIVE_V_END_F0, 0);

	dp_write(base + MMSS_DP_INTF_ACTIVE_V_START_F1, 0);

	dp_write(base + MMSS_DP_INTF_ACTIVE_V_END_F1, 0);

	dp_write(base + MMSS_DP_INTF_POLARITY_CTL, 0);

	wmb(); /* ensure TPG registers are programmed */



	dp_write(base + MMSS_DP_TPG_MAIN_CONTROL, 0x100);

	dp_write(base + MMSS_DP_TPG_VIDEO_CONFIG, 0x5);

	wmb(); /* ensure TPG config is programmed */

	dp_write(base + MMSS_DP_BIST_ENABLE, 0x1);

	dp_write(base + MMSS_DP_TIMING_ENGINE_EN, 0x1);

	wmb(); /* ensure Timing generator is turned on */

}



static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl)
@@ -1309,6 +1359,7 @@ struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io) 
	struct dp_catalog_panel panel = {

		.timing_cfg = dp_catalog_panel_timing_cfg,

		.config_hdr = dp_catalog_panel_config_hdr,

		.tpg_config = dp_catalog_panel_tpg_cfg,

	};



	if (!io) {

drivers/gpu/drm/msm/dp/dp_catalog.h

+10 −0
Original line number Diff line number Diff line
@@ -147,8 +147,18 @@ struct dp_catalog_panel { 


	struct dp_catalog_hdr_data hdr_data;



	/* TPG */

	u32 hsync_period;

	u32 vsync_period;

	u32 display_v_start;

	u32 display_v_end;

	u32 v_sync_width;

	u32 hsync_ctl;

	u32 display_hctl;



	int (*timing_cfg)(struct dp_catalog_panel *panel);

	void (*config_hdr)(struct dp_catalog_panel *panel);

	void (*tpg_config)(struct dp_catalog_panel *panel, bool enable);

};



struct dp_catalog {

drivers/gpu/drm/msm/dp/dp_debug.c

+75 −0
Original line number Diff line number Diff line
@@ -280,6 +280,44 @@ static ssize_t dp_debug_bw_code_write(struct file *file, 
	return len;

}



static ssize_t dp_debug_tpg_write(struct file *file,

		const char __user *user_buff, size_t count, loff_t *ppos)

{

	struct dp_debug_private *debug = file->private_data;

	char buf[SZ_8];

	size_t len = 0;

	u32 tpg_state = 0;



	if (!debug)

		return -ENODEV;



	if (*ppos)

		return 0;



	/* Leave room for termination char */

	len = min_t(size_t, count, SZ_8 - 1);

	if (copy_from_user(buf, user_buff, len))

		goto bail;



	buf[len] = '\0';



	if (kstrtoint(buf, 10, &tpg_state) != 0)

		goto bail;



	tpg_state &= 0x1;

	pr_debug("tpg_state: %d\n", tpg_state);



	if (tpg_state == debug->dp_debug.tpg_state)

		goto bail;



	if (debug->panel)

		debug->panel->tpg_config(debug->panel, tpg_state);



	debug->dp_debug.tpg_state = tpg_state;

bail:

	return len;

}



static ssize_t dp_debug_read_connected(struct file *file,

		char __user *user_buff, size_t count, loff_t *ppos)

{
@@ -552,6 +590,28 @@ static ssize_t dp_debug_bw_code_read(struct file *file, 
	return len;

}



static ssize_t dp_debug_tpg_read(struct file *file,

	char __user *user_buff, size_t count, loff_t *ppos)

{

	struct dp_debug_private *debug = file->private_data;

	char buf[SZ_8];

	u32 len = 0;



	if (!debug)

		return -ENODEV;



	if (*ppos)

		return 0;



	len += snprintf(buf, SZ_8, "%d\n", debug->dp_debug.tpg_state);



	if (copy_to_user(user_buff, buf, len))

		return -EFAULT;



	*ppos += len;

	return len;

}



static const struct file_operations dp_debug_fops = {

	.open = simple_open,

	.read = dp_debug_read_info,
@@ -589,6 +649,12 @@ static const struct file_operations bw_code_fops = { 
	.write = dp_debug_bw_code_write,

};



static const struct file_operations tpg_fops = {

	.open = simple_open,

	.read = dp_debug_tpg_read,

	.write = dp_debug_tpg_write,

};



static int dp_debug_init(struct dp_debug *dp_debug)

{

	int rc = 0;
@@ -669,6 +735,15 @@ static int dp_debug_init(struct dp_debug *dp_debug) 
		goto error_remove_dir;

	}



	file = debugfs_create_file("tpg_ctrl", 0644, dir,

			debug, &tpg_fops);

	if (IS_ERR_OR_NULL(file)) {

		rc = PTR_ERR(file);

		pr_err("[%s] debugfs tpg failed, rc=%d\n",

		       DEBUG_NAME, rc);

		goto error_remove_dir;

	}



	return 0;



error_remove_dir:

drivers/gpu/drm/msm/dp/dp_debug.h

+2 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
 * @vdisplay: used to filter out vdisplay value

 * @hdisplay: used to filter out hdisplay value

 * @vrefresh: used to filter out vrefresh value

 * @tpg_state: specifies whether tpg feature is enabled

 */

struct dp_debug {

	bool debug_en;
@@ -32,6 +33,7 @@ struct dp_debug { 
	int vdisplay;

	int hdisplay;

	int vrefresh;

	bool tpg_state;

};



/**

drivers/gpu/drm/msm/dp/dp_display.c

+4 −0
Original line number Diff line number Diff line
@@ -954,6 +954,10 @@ static int dp_display_enable(struct dp_display *dp_display) 
	}



	rc = dp->ctrl->on(dp->ctrl);



	if (dp->debug->tpg_state)

		dp->panel->tpg_config(dp->panel, true);



	if (!rc)

		dp->power_on = true;

end: