Commit 0487de91 authored Jan 15, 2008 by Dmitri Vorobiev Committed by Ralf Baechle Jan 22, 2008

[MIPS] Malta: Fix reading the PCI clock frequency on big-endian



The JMPRS register on Malta boards keeps a 32-bit CPU-endian
value. The readw() function assumes that the value it reads is a
little-endian 16-bit number. Therefore, using readw() to obtain
the value of the JMPRS register is a mistake. This error leads
to incorrect reading of the PCI clock frequency on big-endian
during board start-up.

Change readw() to __raw_readl().

This was tested by injecting a call to printk() and verifying
that the value of the jmpr variable was consistent with current
setting of the JP4 "PCI CLK" jumper.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent c2a04c4f

arch/mips/mips-boards/malta/malta_setup.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -149,7 +149,7 @@ void __init plat_mem_setup(void)
		/* Check PCI clock */
		{
		unsigned int __iomem jmpr_p = (unsigned int ) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
		int jmpr = (readw(jmpr_p) >> 2) & 0x07;
		int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
		static const int pciclocks[] __initdata = {
		33, 20, 25, 30, 12, 16, 37, 10
		};