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Commit 0438e91b authored by Rajesh Yadav's avatar Rajesh Yadav
Browse files

drm/msm/sde: Add AHB based programming support for igc feature 



Change adds the AHB based igc feature programming support to
color processing module present in CRTC.

Change-Id: Id4865f6f312b2ed72849db2ba5268a7858d6c76b
Signed-off-by: default avatarRajesh Yadav <ryadav@codeaurora.org>
parent ec93afba

drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.c

+49 −0
Original line number Diff line number Diff line
@@ -109,3 +109,52 @@ void sde_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg) 
		&op_mode);



}



void sde_setup_dspp_igcv3(struct sde_hw_dspp *ctx, void *cfg)

{

	struct drm_msm_igc_lut *lut_cfg;

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	int i = 0, j = 0;

	u32 *addr = NULL;

	u32 offset = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable igc feature\n");

		SDE_REG_WRITE(&ctx->hw, IGC_OPMODE_OFF, 0);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_igc_lut)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

				hw_cfg->len, sizeof(struct drm_msm_igc_lut));

		return;

	}



	lut_cfg = hw_cfg->payload;



	for (i = 0; i < IGC_TBL_NUM; i++) {

		addr = lut_cfg->c0 + (i * ARRAY_SIZE(lut_cfg->c0));

		offset = IGC_C0_OFF + (i * sizeof(u32));



		for (j = 0; j < IGC_TBL_LEN; j++) {

			addr[j] &= IGC_DATA_MASK;

			addr[j] |= IGC_DSPP_SEL_MASK(ctx->idx - 1);

			if (j == 0)

				addr[j] |= IGC_INDEX_UPDATE;

			/* IGC lut registers are part of DSPP Top HW block */

			SDE_REG_WRITE(&ctx->hw_top, offset, addr[j]);

		}

	}



	if (lut_cfg->flags & IGC_DITHER_ENABLE) {

		SDE_REG_WRITE(&ctx->hw, IGC_DITHER_OFF,

			lut_cfg->strength & IGC_DITHER_DATA_MASK);

	}



	SDE_REG_WRITE(&ctx->hw, IGC_OPMODE_OFF, IGC_EN);

}

drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.h

+7 −0
Original line number Diff line number Diff line
@@ -22,5 +22,12 @@ 
 * @cfg: pointer to sde_hw_cp_cfg

 */

void sde_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg);

/**

 * sde_setup_dspp_igcv3 - Function for igc v3 version feature

 *                             programming.

 * @ctx: dspp ctx pointer

 * @cfg: pointer to sde_hw_cp_cfg

 */

void sde_setup_dspp_igcv3(struct sde_hw_dspp *ctx, void *cfg);



#endif /* _SDE_HW_COLOR_PROC_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_dspp.c

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) 
						reg_dmav1_setup_dspp_igcv31;

				else

					c->ops.setup_igc =

						NULL; /* TBD: CPU programming */

						sde_setup_dspp_igcv3;

			}

			break;

		case SDE_DSPP_AD: