Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 034705a4 authored by Yakir Yang's avatar Yakir Yang Committed by Russell King
Browse files

drm: bridge/dw_hdmi: separate VLEVCTRL settting into platform driver 



Because of iMX6 & Rockchip have differnet mpll config parameter,
the VLEVCTRL parameter would be different. In this case we should
separate VLEVCTRL setting from the common dw_hdmi driver, config
this parameter in platform driver(dw_hdmi-imx and dw_hdmi-rockchip)

Signed-off-by: default avatarYakir Yang <ykk@rock-chips.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent ca44b9d1

drivers/gpu/drm/bridge/dw_hdmi.c

+7 −7
Original line number Diff line number Diff line
@@ -758,7 +758,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, 
	const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;

	const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg;

	const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr;

	const struct dw_hdmi_sym_term *sym_term = plat_data->sym_term;

	const struct dw_hdmi_phy_config *phy_config = plat_data->phy_config;



	if (prep)

		return -EINVAL;
@@ -829,18 +829,18 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, 
	hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */

	hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);



	for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)

	for (i = 0; phy_config[i].mpixelclock != (~0UL); i++)

		if (hdmi->hdmi_data.video_mode.mpixelclock <=

		    sym_term[i].mpixelclock)

		    phy_config[i].mpixelclock)

			break;



	/* RESISTANCE TERM 133Ohm Cfg */

	hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19);  /* TXTERM */

	hdmi_phy_i2c_write(hdmi, phy_config[i].term, 0x19);  /* TXTERM */

	/* PREEMP Cgf 0.00 */

	hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09);  /* CKSYMTXCTRL */



	hdmi_phy_i2c_write(hdmi, phy_config[i].sym_ctr, 0x09); /* CKSYMTXCTRL */

	/* TX/CK LVL 10 */

	hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */

	hdmi_phy_i2c_write(hdmi, phy_config[i].vlev_ctr, 0x0E); /* VLEVCTRL */



	/* REMOVE CLK TERM */

	hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */

drivers/gpu/drm/imx/dw_hdmi-imx.c

+12 −12
Original line number Diff line number Diff line
@@ -73,10 +73,10 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { 
	}

};



static const struct dw_hdmi_sym_term imx_sym_term[] = {

	/*pixelclk   symbol   term*/

	{ 148500000, 0x800d, 0x0005 },

	{ ~0UL,      0x0000, 0x0000 }

static const struct dw_hdmi_phy_config imx_phy_config[] = {

	/*pixelclk   symbol   term   vlev */

	{ 148500000, 0x800d, 0x0005, 0x01ad},

	{ ~0UL,      0x0000, 0x0000, 0x0000}

};



static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
@@ -139,14 +139,14 @@ static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = { 
static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {

	.mpll_cfg   = imx_mpll_cfg,

	.cur_ctr    = imx_cur_ctr,

	.sym_term = imx_sym_term,

	.phy_config = imx_phy_config,

	.dev_type   = IMX6Q_HDMI,

};



static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {

	.mpll_cfg   = imx_mpll_cfg,

	.cur_ctr    = imx_cur_ctr,

	.sym_term = imx_sym_term,

	.phy_config = imx_phy_config,

	.dev_type   = IMX6DL_HDMI,

};

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

+7 −7
Original line number Diff line number Diff line
@@ -133,12 +133,12 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { 
	}

};



static const struct dw_hdmi_sym_term rockchip_sym_term[] = {

	/*pixelclk   symbol   term*/

	{ 74250000,  0x8009, 0x0004 },

	{ 148500000, 0x8029, 0x0004 },

	{ 297000000, 0x8039, 0x0005 },

	{ ~0UL,	     0x0000, 0x0000 }

static const struct dw_hdmi_phy_config rockchip_phy_config[] = {

	/*pixelclk   symbol   term   vlev*/

	{ 74250000,  0x8009, 0x0004, 0x01ad},

	{ 148500000, 0x8029, 0x0004, 0x01ad},

	{ 297000000, 0x8039, 0x0005, 0x01ad},

	{ ~0UL,	     0x0000, 0x0000, 0x0000}

};



static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
@@ -230,7 +230,7 @@ static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { 
	.mode_valid = dw_hdmi_rockchip_mode_valid,

	.mpll_cfg   = rockchip_mpll_cfg,

	.cur_ctr    = rockchip_cur_ctr,

	.sym_term   = rockchip_sym_term,

	.phy_config = rockchip_phy_config,

	.dev_type   = RK3288_HDMI,

};

include/drm/bridge/dw_hdmi.h

+3 −2
Original line number Diff line number Diff line
@@ -38,17 +38,18 @@ struct dw_hdmi_curr_ctrl { 
	u16 curr[DW_HDMI_RES_MAX];

};



struct dw_hdmi_sym_term {

struct dw_hdmi_phy_config {

	unsigned long mpixelclock;

	u16 sym_ctr;    /*clock symbol and transmitter control*/

	u16 term;       /*transmission termination value*/

	u16 vlev_ctr;   /* voltage level control */

};



struct dw_hdmi_plat_data {

	enum dw_hdmi_devtype dev_type;

	const struct dw_hdmi_mpll_config *mpll_cfg;

	const struct dw_hdmi_curr_ctrl *cur_ctr;

	const struct dw_hdmi_sym_term *sym_term;

	const struct dw_hdmi_phy_config *phy_config;

	enum drm_mode_status (*mode_valid)(struct drm_connector *connector,

					   struct drm_display_mode *mode);

};