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Commit 033b5650 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add initial CS checker support for compute 



- Add some new compute regs
- Add new dispatch packets for evergreen/cayman

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 0d74f86f

drivers/gpu/drm/radeon/evergreen_cs.c

+56 −1
Original line number Diff line number Diff line
@@ -856,7 +856,6 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3 
	case SQ_PGM_START_PS:

	case SQ_PGM_START_HS:

	case SQ_PGM_START_LS:

	case GDS_ADDR_BASE:

	case SQ_CONST_MEM_BASE:

	case SQ_ALU_CONST_CACHE_GS_0:

	case SQ_ALU_CONST_CACHE_GS_1:
@@ -946,6 +945,34 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3 
		}

		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

		break;

	case SX_MEMORY_EXPORT_BASE:

		if (p->rdev->family >= CHIP_CAYMAN) {

			dev_warn(p->dev, "bad SET_CONFIG_REG "

				 "0x%04X\n", reg);

			return -EINVAL;

		}

		r = evergreen_cs_packet_next_reloc(p, &reloc);

		if (r) {

			dev_warn(p->dev, "bad SET_CONFIG_REG "

					"0x%04X\n", reg);

			return -EINVAL;

		}

		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

		break;

	case CAYMAN_SX_SCATTER_EXPORT_BASE:

		if (p->rdev->family < CHIP_CAYMAN) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

				 "0x%04X\n", reg);

			return -EINVAL;

		}

		r = evergreen_cs_packet_next_reloc(p, &reloc);

		if (r) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

					"0x%04X\n", reg);

			return -EINVAL;

		}

		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

		break;

	default:

		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

		return -EINVAL;
@@ -1153,6 +1180,34 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
			return r;

		}

		break;

	case PACKET3_DISPATCH_DIRECT:

		if (pkt->count != 3) {

			DRM_ERROR("bad DISPATCH_DIRECT\n");

			return -EINVAL;

		}

		r = evergreen_cs_track_check(p);

		if (r) {

			dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);

			return r;

		}

		break;

	case PACKET3_DISPATCH_INDIRECT:

		if (pkt->count != 1) {

			DRM_ERROR("bad DISPATCH_INDIRECT\n");

			return -EINVAL;

		}

		r = evergreen_cs_packet_next_reloc(p, &reloc);

		if (r) {

			DRM_ERROR("bad DISPATCH_INDIRECT\n");

			return -EINVAL;

		}

		ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);

		r = evergreen_cs_track_check(p);

		if (r) {

			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);

			return r;

		}

		break;

	case PACKET3_WAIT_REG_MEM:

		if (pkt->count != 5) {

			DRM_ERROR("bad WAIT_REG_MEM\n");

drivers/gpu/drm/radeon/evergreend.h

+2 −0
Original line number Diff line number Diff line
@@ -351,6 +351,7 @@ 
#define		COLOR_BUFFER_SIZE(x)				((x) << 0)

#define		POSITION_BUFFER_SIZE(x)				((x) << 8)

#define		SMX_BUFFER_SIZE(x)				((x) << 16)

#define	SX_MEMORY_EXPORT_BASE				0x9010

#define	SX_MISC						0x28350



#define CB_PERF_CTR0_SEL_0				0x9A20
@@ -1122,6 +1123,7 @@ 
#define CAYMAN_PA_SC_AA_CONFIG				0x28BE0

#define         CAYMAN_MSAA_NUM_SAMPLES_SHIFT           0

#define         CAYMAN_MSAA_NUM_SAMPLES_MASK            0x7

#define CAYMAN_SX_SCATTER_EXPORT_BASE			0x28358

/* cayman packet3 addition */

#define	CAYMAN_PACKET3_DEALLOC_STATE			0x14

drivers/gpu/drm/radeon/r600_cs.c

+9 −0
Original line number Diff line number Diff line
@@ -1200,6 +1200,15 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx 
		}

		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

		break;

	case SX_MEMORY_EXPORT_BASE:

		r = r600_cs_packet_next_reloc(p, &reloc);

		if (r) {

			dev_warn(p->dev, "bad SET_CONFIG_REG "

					"0x%04X\n", reg);

			return -EINVAL;

		}

		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

		break;

	default:

		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

		return -EINVAL;

drivers/gpu/drm/radeon/radeon_drv.c

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ 
 *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs

 *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query

 *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query

 *   2.10.0 - fusion 2D tiling

 *   2.10.0 - fusion 2D tiling, initial compute support for the CS checker

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	10

drivers/gpu/drm/radeon/reg_srcs/cayman

+2 −0
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ cayman 0x9400 
0x0002834C PA_SC_VPORT_ZMAX_15

0x00028350 SX_MISC

0x00028354 SX_SURFACE_SYNC

0x0002835C SX_SCATTER_EXPORT_SIZE

0x00028380 SQ_VTX_SEMANTIC_0

0x00028384 SQ_VTX_SEMANTIC_1

0x00028388 SQ_VTX_SEMANTIC_2
@@ -432,6 +433,7 @@ cayman 0x9400 
0x00028700 SPI_STACK_MGMT

0x00028704 SPI_WAVE_MGMT_1

0x00028708 SPI_WAVE_MGMT_2

0x00028720 GDS_ADDR_BASE

0x00028724 GDS_ADDR_SIZE

0x00028780 CB_BLEND0_CONTROL

0x00028784 CB_BLEND1_CONTROL