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Commit 02fdfd70 authored by Murali Karicheri's avatar Murali Karicheri Committed by Michael Turquette
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clk: keystone: add support for post divider register for main pll 



Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.

Signed-off-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
parent 91990d21

Documentation/devicetree/bindings/clock/keystone-pll.txt

+4 −4
Original line number Diff line number Diff line
@@ -15,8 +15,8 @@ Required properties: 
- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"

- clocks : parent clock phandle

- reg - pll control0 and pll multipler registers

- reg-names : control and multiplier. The multiplier is applicable only for

		main pll clock

- reg-names : control, multiplier and post-divider. The multiplier and

		post-divider registers are applicable only for main pll clock

- fixed-postdiv : fixed post divider value. If absent, use clkod register bits

		for postdiv
@@ -25,8 +25,8 @@ Example: 
		#clock-cells = <0>;

		compatible = "ti,keystone,main-pll-clock";

		clocks = <&refclksys>;

		reg = <0x02620350 4>, <0x02310110 4>;

		reg-names = "control", "multiplier";

		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;

		reg-names = "control", "multiplier", "post-divider";

		fixed-postdiv = <2>;

	};

drivers/clk/keystone/pll.c

+18 −2
Original line number Diff line number Diff line
@@ -37,7 +37,8 @@ 
 *	Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL

 *	or PA PLL available on keystone2. These PLLs are controlled by

 *	this register. Main PLL is controlled by a PLL controller.

 * @pllm: PLL register map address

 * @pllm: PLL register map address for multiplier bits

 * @pllod: PLL register map address for post divider bits

 * @pll_ctl0: PLL controller map address

 * @pllm_lower_mask: multiplier lower mask

 * @pllm_upper_mask: multiplier upper mask
@@ -53,6 +54,7 @@ struct clk_pll_data { 
	u32 phy_pllm;

	u32 phy_pll_ctl0;

	void __iomem *pllm;

	void __iomem *pllod;

	void __iomem *pll_ctl0;

	u32 pllm_lower_mask;

	u32 pllm_upper_mask;
@@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, 
		/* read post divider from od bits*/

		postdiv = ((val & pll_data->clkod_mask) >>

				 pll_data->clkod_shift) + 1;

	else

	else if (pll_data->pllod) {

		postdiv = readl(pll_data->pllod);

		postdiv = ((postdiv & pll_data->clkod_mask) >>

				pll_data->clkod_shift) + 1;

	} else

		postdiv = pll_data->postdiv;



	rate /= (prediv + 1);
@@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) 
		/* assume the PLL has output divider register bits */

		pll_data->clkod_mask = CLKOD_MASK;

		pll_data->clkod_shift = CLKOD_SHIFT;



		/*

		 * Check if there is an post-divider register. If not

		 * assume od bits are part of control register.

		 */

		i = of_property_match_string(node, "reg-names",

					     "post-divider");

		pll_data->pllod = of_iomap(node, i);

	}



	i = of_property_match_string(node, "reg-names", "control");

	pll_data->pll_ctl0 = of_iomap(node, i);

	if (!pll_data->pll_ctl0) {

		pr_err("%s: ioremap failed\n", __func__);

		iounmap(pll_data->pllod);

		goto out;

	}
@@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) 
		pll_data->pllm = of_iomap(node, i);

		if (!pll_data->pllm) {

			iounmap(pll_data->pll_ctl0);

			iounmap(pll_data->pllod);

			goto out;

		}

	}