Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 02c9f7e3 authored by Kenneth Graunke's avatar Kenneth Graunke Committed by Daniel Vetter
Browse files

drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround. 



On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.

Documented on the BSpec 3D workarounds page.

Reviewed-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
[vsyrjala: add chv w/a note too]
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 884ceace

drivers/gpu/drm/i915/intel_ringbuffer.c

+9 −0
Original line number Diff line number Diff line
@@ -406,6 +406,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, 
{

	u32 flags = 0;

	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;

	int ret;



	flags |= PIPE_CONTROL_CS_STALL;
@@ -422,6 +423,14 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, 
		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_QW_WRITE;

		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;



		/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */

		ret = gen8_emit_pipe_control(ring,

					     PIPE_CONTROL_CS_STALL |

					     PIPE_CONTROL_STALL_AT_SCOREBOARD,

					     0);

		if (ret)

			return ret;

	}



	return gen8_emit_pipe_control(ring, flags, scratch_addr);