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Commit 0223afc3 authored by Maulik Shah's avatar Maulik Shah Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Update QoS values for sdm670 



Different devices like usb, gpu, sde, sdhc and ufs uses different
QoS values. Based on exit latencies on sdm670, these all values
are blocking deeper LPMs and allows only WFI mode.

For scenarios where one request is already active that allow only WFI
mode LPM and new request is added that also allows only WFI mode but
the value is different.

For such cases QoS framework still notifies cpuidle to wake up CPU from
idle to reselect new mode based on new aggregated QoS value.

Update QoS values to same (WFI exit latency + 1) for all devices blocking
same LPM mode to avoid such wake ups.

Change-Id: I81b71d7e72584373dcc4b125ee4440a3c3cbe289
Signed-off-by: default avatarMaulik Shah <mkshah@codeaurora.org>
parent 463d8c28

arch/arm64/boot/dts/qcom/sdm670-gpu.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -122,8 +122,8 @@ 
		cache-slices = <&llcc 12>, <&llcc 11>;



		/* CPU latency parameter */

		qcom,pm-qos-active-latency = <899>;

		qcom,pm-qos-wakeup-latency = <899>;

		qcom,pm-qos-active-latency = <67>;

		qcom,pm-qos-wakeup-latency = <67>;



		/* Enable context aware freq. scaling */

		qcom,enable-ca-jump;

arch/arm64/boot/dts/qcom/sdm670-sde.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -399,7 +399,7 @@ 
		qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>;



		qcom,mdss-rot-qos-cpu-mask = <0xf>;

		qcom,mdss-rot-qos-cpu-dma-latency = <75>;

		qcom,mdss-rot-qos-cpu-dma-latency = <67>;



		qcom,mdss-default-ot-rd-limit = <32>;

		qcom,mdss-default-ot-wr-limit = <32>;

arch/arm64/boot/dts/qcom/sdm670-usb.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
};



&usb0 {

	qcom,pm-qos-latency = <601>; /* CPU-CLUSTER-WFI-LVL latency +1 */

	qcom,pm-qos-latency = <67>; /* CPU WFI latency + 1 */

	extcon = <0>, <0>, <&eud>, <0>, <0>;

};

arch/arm64/boot/dts/qcom/sdm670.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -1930,7 +1930,7 @@ 


		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x3f 0xC0>;

		qcom,pm-qos-cpu-group-latency-us = <70 70>;

		qcom,pm-qos-cpu-group-latency-us = <67 67>;

		qcom,pm-qos-default-cpu = <0>;



		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
@@ -2370,8 +2370,8 @@ 
		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <70 70>;

		qcom,pm-qos-cpu-groups = <0x3f 0xc0>;

		qcom,pm-qos-cmdq-latency-us = <70 70>, <70 70>;

		qcom,pm-qos-legacy-latency-us = <70 70>, <70 70>;

		qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;

		qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;



		clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,

			<&clock_gcc GCC_SDCC1_APPS_CLK>,
@@ -2441,9 +2441,9 @@ 


		/* PM QoS */

		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <70 70>;

		qcom,pm-qos-irq-latency = <67 67>;

		qcom,pm-qos-cpu-groups = <0x3f 0xc0>;

		qcom,pm-qos-legacy-latency-us = <70 70>, <70 70>;

		qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;



		clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,

			<&clock_gcc GCC_SDCC2_APPS_CLK>;