Loading Documentation/networking/ip-sysctl.txt +0 −6 Original line number Diff line number Diff line Loading @@ -48,12 +48,6 @@ min_adv_mss - INTEGER The advertised MSS depends on the first hop route MTU, but will never be lower than this setting. rt_cache_rebuild_count - INTEGER The per net-namespace route cache emergency rebuild threshold. Any net-namespace having its route cache rebuilt due to a hash bucket chain being too long more than this many times will have its route caching disabled IP Fragmentation: ipfrag_high_thresh - INTEGER Loading drivers/bcma/Kconfig +2 −2 Original line number Diff line number Diff line Loading @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS config BCMA_SFLASH bool depends on BCMA_DRIVER_MIPS && BROKEN depends on BCMA_DRIVER_MIPS default y config BCMA_NFLASH bool depends on BCMA_DRIVER_MIPS && BROKEN depends on BCMA_DRIVER_MIPS default y config BCMA_DRIVER_GMAC_CMN Loading drivers/bcma/bcma_private.h +2 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,7 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); #ifdef CONFIG_BCMA_SFLASH /* driver_chipcommon_sflash.c */ int bcma_sflash_init(struct bcma_drv_cc *cc); extern struct platform_device bcma_sflash_dev; #else static inline int bcma_sflash_init(struct bcma_drv_cc *cc) { Loading @@ -65,6 +66,7 @@ static inline int bcma_sflash_init(struct bcma_drv_cc *cc) #ifdef CONFIG_BCMA_NFLASH /* driver_chipcommon_nflash.c */ int bcma_nflash_init(struct bcma_drv_cc *cc); extern struct platform_device bcma_nflash_dev; #else static inline int bcma_nflash_init(struct bcma_drv_cc *cc) { Loading drivers/bcma/driver_chipcommon_nflash.c +25 −3 Original line number Diff line number Diff line Loading @@ -5,15 +5,37 @@ * Licensed under the GNU/GPL. See COPYING for details. */ #include <linux/platform_device.h> #include <linux/bcma/bcma.h> #include <linux/bcma/bcma_driver_chipcommon.h> #include <linux/delay.h> #include "bcma_private.h" struct platform_device bcma_nflash_dev = { .name = "bcma_nflash", .num_resources = 0, }; /* Initialize NAND flash access */ int bcma_nflash_init(struct bcma_drv_cc *cc) { bcma_err(cc->core->bus, "NAND flash support is broken\n"); struct bcma_bus *bus = cc->core->bus; if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 && cc->core->id.rev != 0x38) { bcma_err(bus, "NAND flash on unsupported board!\n"); return -ENOTSUPP; } if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) { bcma_err(bus, "NAND flash not present according to ChipCommon\n"); return -ENODEV; } cc->nflash.present = true; /* Prepare platform device, but don't register it yet. It's too early, * malloc (required by device_private_init) is not available yet. */ bcma_nflash_dev.dev.platform_data = &cc->nflash; return 0; } drivers/bcma/driver_chipcommon_pmu.c +2 −2 Original line number Diff line number Diff line Loading @@ -101,7 +101,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable) bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); } void bcma_pmu_workarounds(struct bcma_drv_cc *cc) static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; Loading Loading @@ -257,7 +257,7 @@ static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) } /* query bus clock frequency for PMU-enabled chipcommon */ u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; Loading Loading
Documentation/networking/ip-sysctl.txt +0 −6 Original line number Diff line number Diff line Loading @@ -48,12 +48,6 @@ min_adv_mss - INTEGER The advertised MSS depends on the first hop route MTU, but will never be lower than this setting. rt_cache_rebuild_count - INTEGER The per net-namespace route cache emergency rebuild threshold. Any net-namespace having its route cache rebuilt due to a hash bucket chain being too long more than this many times will have its route caching disabled IP Fragmentation: ipfrag_high_thresh - INTEGER Loading
drivers/bcma/Kconfig +2 −2 Original line number Diff line number Diff line Loading @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS config BCMA_SFLASH bool depends on BCMA_DRIVER_MIPS && BROKEN depends on BCMA_DRIVER_MIPS default y config BCMA_NFLASH bool depends on BCMA_DRIVER_MIPS && BROKEN depends on BCMA_DRIVER_MIPS default y config BCMA_DRIVER_GMAC_CMN Loading
drivers/bcma/bcma_private.h +2 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,7 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); #ifdef CONFIG_BCMA_SFLASH /* driver_chipcommon_sflash.c */ int bcma_sflash_init(struct bcma_drv_cc *cc); extern struct platform_device bcma_sflash_dev; #else static inline int bcma_sflash_init(struct bcma_drv_cc *cc) { Loading @@ -65,6 +66,7 @@ static inline int bcma_sflash_init(struct bcma_drv_cc *cc) #ifdef CONFIG_BCMA_NFLASH /* driver_chipcommon_nflash.c */ int bcma_nflash_init(struct bcma_drv_cc *cc); extern struct platform_device bcma_nflash_dev; #else static inline int bcma_nflash_init(struct bcma_drv_cc *cc) { Loading
drivers/bcma/driver_chipcommon_nflash.c +25 −3 Original line number Diff line number Diff line Loading @@ -5,15 +5,37 @@ * Licensed under the GNU/GPL. See COPYING for details. */ #include <linux/platform_device.h> #include <linux/bcma/bcma.h> #include <linux/bcma/bcma_driver_chipcommon.h> #include <linux/delay.h> #include "bcma_private.h" struct platform_device bcma_nflash_dev = { .name = "bcma_nflash", .num_resources = 0, }; /* Initialize NAND flash access */ int bcma_nflash_init(struct bcma_drv_cc *cc) { bcma_err(cc->core->bus, "NAND flash support is broken\n"); struct bcma_bus *bus = cc->core->bus; if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 && cc->core->id.rev != 0x38) { bcma_err(bus, "NAND flash on unsupported board!\n"); return -ENOTSUPP; } if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) { bcma_err(bus, "NAND flash not present according to ChipCommon\n"); return -ENODEV; } cc->nflash.present = true; /* Prepare platform device, but don't register it yet. It's too early, * malloc (required by device_private_init) is not available yet. */ bcma_nflash_dev.dev.platform_data = &cc->nflash; return 0; }
drivers/bcma/driver_chipcommon_pmu.c +2 −2 Original line number Diff line number Diff line Loading @@ -101,7 +101,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable) bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); } void bcma_pmu_workarounds(struct bcma_drv_cc *cc) static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; Loading Loading @@ -257,7 +257,7 @@ static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) } /* query bus clock frequency for PMU-enabled chipcommon */ u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; Loading