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Commit 00b0af5b authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tony Lindgren
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ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance 



Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent b700f42c

arch/arm/boot/dts/dra7xx-clocks.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -1173,6 +1173,14 @@ 
		ti,bit-shift = <8>;

	};



	optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {

		compatible = "ti,gate-clock";

		clocks = <&sys_32k_ck>;

		#clock-cells = <0>;

		reg = <0x13b8>;

		ti,bit-shift = <8>;

	};



	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {

		compatible = "ti,divider-clock";

		clocks = <&apll_pcie_ck>;
@@ -1191,6 +1199,14 @@ 
		ti,bit-shift = <9>;

	};



	optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {

		compatible = "ti,gate-clock";

		clocks = <&apll_pcie_ck>;

		#clock-cells = <0>;

		reg = <0x13b8>;

		ti,bit-shift = <9>;

	};



	optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {

		compatible = "ti,gate-clock";

		clocks = <&optfclk_pciephy_div>;
@@ -1199,6 +1215,14 @@ 
		ti,bit-shift = <10>;

	};



	optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {

		compatible = "ti,gate-clock";

		clocks = <&optfclk_pciephy_div>;

		#clock-cells = <0>;

		reg = <0x13b8>;

		ti,bit-shift = <10>;

	};



	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";