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Commit 00644d3a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: mdm: Add initial device node support for MDM9650"

parents 937bf2eb b444e832
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+7 −6
Original line number Diff line number Diff line
@@ -128,8 +128,8 @@ SoCs:
- MDM9640
  compatible = "qcom,mdm9640"

- MDMCALIFORNIUM
  compatible = "qcom,mdmcalifornium"
- MDM9650
  compatible = "qcom,mdm9650"

- SDXPOORWILLS
  compatible = "qcom,sdxpoorwills"
@@ -190,6 +190,9 @@ Generic board variants:
- IPC device:
  compatible = "qcom,ipc"

- TTP device:
  compatible = "qcom,ttp"

Boards (SoC type + board variant):

compatible = "qcom,apq8016"
@@ -356,10 +359,8 @@ compatible = "qcom,msmvpipa-sim"
compatible = "qcom,mdm9607-rumi"
compatible = "qcom,mdm9607-cdp"
compatible = "qcom,mdm9607-mtp"
compatible = "qcom,mdmcalifornium-rumi"
compatible = "qcom,mdmcalifornium-sim"
compatible = "qcom,mdmcalifornium-cdp"
compatible = "qcom,mdmcalifornium-mtp"
compatible = "qcom,mdm9650-mtp"
compatible = "qcom,mdm9650-ttp"
compatible = "qcom,apq8009-cdp"
compatible = "qcom,apq8009-mtp"
compatible = "qcom,sdxpoorwills-rumi"
+139 −0
Original line number Diff line number Diff line
QTI MDM9650 TLMM block

This binding describes the Top Level Mode Multiplexer block found in the
MDM9650 platform.

- compatible:
	Usage: required
	Value type: <string>
	Definition: must be "qcom,mdm9650-pinctrl"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: the base address and size of the TLMM register space.

- interrupts:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: should specify the TLMM summary IRQ.

- interrupt-controller:
	Usage: required
	Value type: <none>
	Definition: identifies this node as an interrupt controller

- #interrupt-cells:
	Usage: required
	Value type: <u32>
	Definition: must be 2. Specifying the pin number and flags, as defined
		    in <dt-bindings/interrupt-controller/irq.h>

- gpio-controller:
	Usage: required
	Value type: <none>
	Definition: identifies this node as a gpio controller

- #gpio-cells:
	Usage: required
	Value type: <u32>
	Definition: must be 2. Specifying the pin number and flags, as defined
		    in <dt-bindings/gpio/gpio.h>

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.


PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.


The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:

- pins:
	Usage: required
	Value type: <string-array>
	Definition: List of gpio pins affected by the properties specified in
		    this subnode.

- function:
	Usage: required
	Value type: <string>
	Definition: Specify the alternative function to be configured for the
		    specified pins.

- bias-disable:
	Usage: optional
	Value type: <none>
	Definition: The specified pins should be configued as no pull.

- bias-pull-down:
	Usage: optional
	Value type: <none>
	Definition: The specified pins should be configued as pull down.

- bias-pull-up:
	Usage: optional
	Value type: <none>
	Definition: The specified pins should be configued as pull up.

- output-high:
	Usage: optional
	Value type: <none>
	Definition: The specified pins are configured in output mode, driven
		    high.

- output-low:
	Usage: optional
	Value type: <none>
	Definition: The specified pins are configured in output mode, driven
		    low.

- drive-strength:
	Usage: optional
	Value type: <u32>
	Definition: Selects the drive strength for the specified pins, in mA.

Example:

	tlmm_pinmux: pinctrl@1000000 {
		compatible = "qcom,mdm9650-pinctrl";
		reg = <0x1000000 0x300000>;
		interrupts = <0 208 0>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;

		uart1_console_active: uart1_console_active {
			mux {
				pins = "gpio0", "gpio1";
				function = "blsp_uart1";
			};

			config {
				pins = "gpio0", "gpio1";
				drive-strength = <2>;
				bias-disable;
			};
		};
	};
+5 −0
Original line number Diff line number Diff line
@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_SDXPOORWILLS) += sdxpoorwills-rumi.dtb \
	sdxpoorwills-pcie-ep-cdp.dtb \
	sdxpoorwills-pcie-ep-mtp.dtb

dtb-$(CONFIG_ARCH_MDM9650) += mdm9650-nand-mtp.dtb \
	mdm9650-ttp.dtb \
	mdm9650-v1.1-nand-mtp.dtb \
	mdm9650-v1.1-nand-cv2x.dtb

targets += dtbs
targets += $(addprefix ../, $(dtb-y))

+498 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/ {
	aliases {
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		spi1 = &spi_1;
		spi2 = &spi_2;
		spi3 = &spi_3;
		spi4 = &spi_4;
	};
};

&soc {
	dma_blsp1: qcom,sps-dma@7884000{ /* BLSP1 */
		#dma-cells = <4>;
		compatible = "qcom,sps-dma";
		reg = <0x7884000 0x23000>;
		interrupts = <0 238 0>;
		qcom,summing-threshold = <0x10>;
	};

	i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "qup_phys_addr";
		reg = <0x78b5000 0x600>;
		interrupt-names = "qup_irq";
		interrupts = <0 95 0>;
		dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
			<&dma_blsp1 9 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_1_active>;
		pinctrl-1 = <&i2c_1_sleep>;
		status = "disabled";
	};

	i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "qup_phys_addr";
		reg = <0x78b6000 0x600>;
		interrupt-names = "qup_irq";
		interrupts = <0 96 0>;
		dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
			<&dma_blsp1 11 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_2_active>;
		pinctrl-1 = <&i2c_2_sleep>;
		status = "disabled";
	};

	i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "qup_phys_addr";
		reg = <0x78b7000 0x600>;
		interrupt-names = "qup_irq";
		interrupts = <0 97 0>;
		dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
			<&dma_blsp1 13 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_3_active>;
		pinctrl-1 = <&i2c_3_sleep>;
		status = "disabled";

		wcd9xxx_codec@d{
			compatible = "qcom,tasha-i2c-pgd";
			reg = <0x0d>;

			interrupt-parent = <&wcd9xxx_intc>;
			interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
				      17 18 19 20 21 22 23 24 25 26 27 28 29
				      30>;

			qcom,cdc-reset-gpio = <&tlmm_pinmux 90 0>;

			clock-names = "wcd_clk";
			clocks = <&clock_audio clk_audio_lpass_mclk>;

			qcom,msm-mbhc-hphl-swh = <0>;
			qcom,msm-mbhc-gnd-swh = <0>;

			cdc-vdd-buck-supply = <&codec_buck_vreg>;
			qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
			qcom,cdc-vdd-buck-current = <650000>;

			cdc-buck-sido-supply = <&codec_buck_vreg>;
			qcom,cdc-buck-sido-voltage = <1800000 1800000>;
			qcom,cdc-buck-sido-current = <200000>;

			cdc-vdd-tx-h-supply = <&pmd9650_l6>;
			qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
			qcom,cdc-vdd-tx-h-current = <25000>;

			cdc-vdd-rx-h-supply = <&pmd9650_l6>;
			qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
			qcom,cdc-vdd-rx-h-current = <25000>;

			cdc-vddpx-1-supply = <&pmd9650_l6>;
			qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
			qcom,cdc-vddpx-1-current = <10000>;

			qcom,cdc-static-supplies = "cdc-vdd-buck",
						   "cdc-buck-sido",
						   "cdc-vdd-tx-h",
						   "cdc-vdd-rx-h",
						   "cdc-vddpx-1";

			qcom,cdc-micbias1-mv = <1800>;
			qcom,cdc-micbias2-mv = <1800>;
			qcom,cdc-micbias3-mv = <1800>;
			qcom,cdc-micbias4-mv = <1800>;
			qcom,cdc-mclk-clk-rate = <12288000>;
			qcom,cdc-dmic-sample-rate = <4800000>;

			swr_master {
				compatible = "qcom,swr-wcd";
				#address-cells = <2>;
				#size-cells = <0>;

				wsa881x_211: wsa881x@20170211 {
					compatible = "qcom,wsa881x";
					reg = <0x00 0x20170211>;
					qcom,spkr-sd-n-gpio =
						<&tlmm_pinmux 81 0>;
				};

				wsa881x_212: wsa881x@20170212 {
					compatible = "qcom,wsa881x";
					reg = <0x00 0x20170212>;
					qcom,spkr-sd-n-gpio =
						<&tlmm_pinmux 81 0>;
				};

				wsa881x_213: wsa881x@21170213 {
					compatible = "qcom,wsa881x";
					reg = <0x00 0x21170213>;
					qcom,spkr-sd-n-gpio =
						<&tlmm_pinmux 81 0>;
				};

				wsa881x_214: wsa881x@21170214 {
					compatible = "qcom,wsa881x";
					reg = <0x00 0x21170214>;
					qcom,spkr-sd-n-gpio =
						<&tlmm_pinmux 81 0>;
				};
			};
		};
	};

	i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "qup_phys_addr";
		reg = <0x78b8000 0x600>;
		interrupt-names = "qup_irq";
		interrupts = <0 98 0>;
		dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
			<&dma_blsp1 15 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_4_active>;
		pinctrl-1 = <&i2c_4_sleep>;
		status = "disabled";
	};


	spi_1: spi@78b5000 { /* BLSP1 QUP1 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x078b5000 0x600>,
		      <0x7884000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 95 0>, <0 238 0>;
		spi-max-frequency = <19200000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <8>;
		qcom,bam-producer-pipe-index = <9>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_1_active>;
		pinctrl-1 = <&spi_1_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
		status = "disabled";
	};

	spi_2: spi@78b6000 { /* BLSP1 QUP2 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b6000 0x600>,
		      <0x7884000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 96 0>, <0 238 0>;
		spi-max-frequency = <19200000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <10>;
		qcom,bam-producer-pipe-index = <11>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_2_active>;
		pinctrl-1 = <&spi_2_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;
		status = "disabled";
	};

	spi_3: spi@78b7000 { /* BLSP1 QUP3 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x078b7000 0x600>,
		      <0x7884000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 97 0>, <0 238 0>;
		spi-max-frequency = <19200000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <12>;
		qcom,bam-producer-pipe-index = <13>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_3_active>;
		pinctrl-1 = <&spi_3_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>;
		status = "disabled";
	};

	spi_4: spi@78b8000 { /* BLSP1 QUP4 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x078b8000 0x600>,
		      <0x7884000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 98 0>, <0 238 0>;
		spi-max-frequency = <19200000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <14>;
		qcom,bam-producer-pipe-index = <15>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_4_active>;
		pinctrl-1 = <&spi_4_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>;
		status = "disabled";
	};

	blsp1_uart1_hs: uart@78af000 { /* BLSP1 UART1 */
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78af000 0x200>,
		    <0x7884000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart1_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 107 0
			    1 &intc 0 238 0
			    2 &tlmm_pinmux 1 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xFD>;

		qcom,bam-tx-ep-pipe-index = <0>;
		qcom,bam-rx-ep-pipe-index = <1>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart1_sleep>;
		pinctrl-1 = <&blsp1_uart1_active>;

		qcom,msm-bus,name = "buart1";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp1_uart2_hs: uart@78b0000 { /* BLSP1 UART2 */
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78b0000 0x200>,
		    <0x7884000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart2_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 108 0
			    1 &intc 0 238 0
			    2 &tlmm_pinmux 5 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xFD>;

		qcom,bam-tx-ep-pipe-index = <2>;
		qcom,bam-rx-ep-pipe-index = <3>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart2_sleep>;
		pinctrl-1 = <&blsp1_uart2_active>;

		qcom,msm-bus,name = "buart2";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp1_uart3_hs: uart@78b1000 { /* BLSP1 UART3 */
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78b1000 0x200>,
		    <0x7884000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart3_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 109 0
			    1 &intc 0 238 0
			    2 &tlmm_pinmux 9 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xFD>;

		qcom,bam-tx-ep-pipe-index = <4>;
		qcom,bam-rx-ep-pipe-index = <5>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart3_sleep>;
		pinctrl-1 = <&blsp1_uart3_active>;

		qcom,msm-bus,name = "buart3";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp1_uart4_hs: uart@78b2000 { /* BLSP1 UART4 */
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78b2000 0x200>,
		    <0x7884000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart4_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 110 0
			    1 &intc 0 238 0
			    2 &tlmm_pinmux 13 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xFD>;

		qcom,bam-tx-ep-pipe-index = <6>;
		qcom,bam-rx-ep-pipe-index = <7>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>,
		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart4_sleep>;
		pinctrl-1 = <&blsp1_uart4_active>;

		qcom,msm-bus,name = "buart4";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp1_uart4b_hs: uart@78b2000 { /* BLSP1 UART4b */
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78b2000 0x200>,
		    <0x7884000 0x23000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart4_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 110 0
			    1 &intc 0 238 0
			    2 &tlmm_pinmux 17 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xFD>;

		qcom,bam-tx-ep-pipe-index = <6>;
		qcom,bam-rx-ep-pipe-index = <7>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>,
		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart4b_sleep>;
		pinctrl-1 = <&blsp1_uart4b_active>;

		qcom,msm-bus,name = "buart4b";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};
};
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