Loading arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +1 −31 Original line number Diff line number Diff line Loading @@ -42,23 +42,14 @@ #define S3C2443_PLLCON_OFF (1<<24) #define S3C2443_CLKSRC_I2S_EXT (1<<14) #define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14) #define S3C2443_CLKSRC_I2S_EPLLREF (2<<14) #define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) #define S3C2443_CLKSRC_I2S_MASK (3<<14) #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) #define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) #define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) #define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) #define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) #define S3C2443_CLKDIV0_DVS (1<<13) #define S3C2443_CLKDIV0_HALF_HCLK (1<<3) #define S3C2443_CLKDIV0_HALF_PCLK (1<<2) Loading @@ -81,28 +72,7 @@ #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) /* S3C2443_CLKDIV1 */ #define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26) #define S3C2443_CLKDIV1_CAMDIV_SHIFT (26) #define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24) #define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24) #define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16) #define S3C2443_CLKDIV1_DISPDIV_SHIFT (16) #define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12) #define S3C2443_CLKDIV1_I2SDIV_SHIFT (12) #define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8) #define S3C2443_CLKDIV1_UARTDIV_SHIFT (8) #define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6) #define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6) #define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4) #define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4) /* S3C2443_CLKDIV1 removed, only used in clock.c code */ #define S3C2443_CLKCON_NAND Loading arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c→arch/arm/mach-s3c2440/s3c2440-pll-12000000.c +1 −1 Original line number Diff line number Diff line /* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c /* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c * * Copyright (c) 2006-2007 Simtec Electronics * http://armlinux.simtec.co.uk/ Loading arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c→arch/arm/mach-s3c2440/s3c2440-pll-16934400.c +1 −1 Original line number Diff line number Diff line /* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c /* arch/arm/mach-s3c2440/s3c2440-pll-16934400.c * * Copyright (c) 2006-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ Loading arch/arm/mach-s3c2443/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -7,6 +7,7 @@ config CPU_S3C2443 depends on ARCH_S3C2410 select S3C2443_DMA if S3C2410_DMA select CPU_LLSERIAL_S3C2440 select SAMSUNG_CLKSRC help Support for the S3C2443 SoC from the S3C24XX line Loading arch/arm/mach-s3c2443/clock.c +259 −558 File changed.Preview size limit exceeded, changes collapsed. Show changes Loading
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +1 −31 Original line number Diff line number Diff line Loading @@ -42,23 +42,14 @@ #define S3C2443_PLLCON_OFF (1<<24) #define S3C2443_CLKSRC_I2S_EXT (1<<14) #define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14) #define S3C2443_CLKSRC_I2S_EPLLREF (2<<14) #define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) #define S3C2443_CLKSRC_I2S_MASK (3<<14) #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) #define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) #define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) #define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) #define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) #define S3C2443_CLKDIV0_DVS (1<<13) #define S3C2443_CLKDIV0_HALF_HCLK (1<<3) #define S3C2443_CLKDIV0_HALF_PCLK (1<<2) Loading @@ -81,28 +72,7 @@ #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) /* S3C2443_CLKDIV1 */ #define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26) #define S3C2443_CLKDIV1_CAMDIV_SHIFT (26) #define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24) #define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24) #define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16) #define S3C2443_CLKDIV1_DISPDIV_SHIFT (16) #define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12) #define S3C2443_CLKDIV1_I2SDIV_SHIFT (12) #define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8) #define S3C2443_CLKDIV1_UARTDIV_SHIFT (8) #define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6) #define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6) #define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4) #define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4) /* S3C2443_CLKDIV1 removed, only used in clock.c code */ #define S3C2443_CLKCON_NAND Loading
arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c→arch/arm/mach-s3c2440/s3c2440-pll-12000000.c +1 −1 Original line number Diff line number Diff line /* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c /* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c * * Copyright (c) 2006-2007 Simtec Electronics * http://armlinux.simtec.co.uk/ Loading
arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c→arch/arm/mach-s3c2440/s3c2440-pll-16934400.c +1 −1 Original line number Diff line number Diff line /* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c /* arch/arm/mach-s3c2440/s3c2440-pll-16934400.c * * Copyright (c) 2006-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ Loading
arch/arm/mach-s3c2443/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -7,6 +7,7 @@ config CPU_S3C2443 depends on ARCH_S3C2410 select S3C2443_DMA if S3C2410_DMA select CPU_LLSERIAL_S3C2440 select SAMSUNG_CLKSRC help Support for the S3C2443 SoC from the S3C24XX line Loading
arch/arm/mach-s3c2443/clock.c +259 −558 File changed.Preview size limit exceeded, changes collapsed. Show changes