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Commit 00194ecf authored by Imre Deak's avatar Imre Deak Committed by Greg Kroah-Hartman
Browse files

drm/i915/gen8+: Add RC6 CTX corruption WA 



commit 7e34f4e4aad3fd34c02b294a3cf2321adf5b4438 upstream.

In some circumstances the RC6 context can get corrupted. We can detect
this and take the required action, that is disable RC6 and runtime PM.
The HW recovers from the corrupted state after a system suspend/resume
cycle, so detect the recovery and re-enable RC6 and runtime PM.

v2: rebase (Mika)
v3:
- Move intel_suspend_gt_powersave() to the end of the GEM suspend
  sequence.
- Add commit message.
v4:
- Rebased on intel_uncore_forcewake_put(i915->uncore, ...) API
  change.
v5:
- Rebased on latest upstream gt_pm refactoring.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ebd6ded1

drivers/gpu/drm/i915/i915_drv.c

+3 −0
Original line number Diff line number Diff line
@@ -1470,6 +1470,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 
	disable_rpm_wakeref_asserts(dev_priv);



	intel_display_set_init_power(dev_priv, false);

	i915_rc6_ctx_wa_suspend(dev_priv);



	fw_csr = !IS_BROXTON(dev_priv) &&

		suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
@@ -1706,6 +1707,8 @@ static int i915_drm_resume_early(struct drm_device *dev) 
	else

		intel_display_set_init_power(dev_priv, true);



	i915_rc6_ctx_wa_resume(dev_priv);



	enable_rpm_wakeref_asserts(dev_priv);



out:

drivers/gpu/drm/i915/i915_drv.h

+5 −2
Original line number Diff line number Diff line
@@ -1228,6 +1228,7 @@ struct intel_gen6_power_mgmt { 
	bool client_boost;



	bool enabled;

	bool ctx_corrupted;

	struct delayed_work autoenable_work;

	unsigned boosts;
@@ -2695,11 +2696,13 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg) 
/* Early gen2 have a totally busted CS tlb and require pinned batches. */

#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))



#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\

	(IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) == 9)



/* WaRsDisableCoarsePowerGating:skl,bxt */

#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \

	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \

	 IS_SKL_GT3(dev_priv) || \

	 IS_SKL_GT4(dev_priv))

	 (INTEL_GEN(dev_priv) == 9))



/*

 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts

drivers/gpu/drm/i915/i915_gem.c

+6 −0
Original line number Diff line number Diff line
@@ -2763,6 +2763,12 @@ i915_gem_idle_work_handler(struct work_struct *work) 


	if (INTEL_GEN(dev_priv) >= 6)

		gen6_rps_idle(dev_priv);



	if (NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)) {

		i915_rc6_ctx_wa_check(dev_priv);

		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	}



	intel_runtime_pm_put(dev_priv);

out_unlock:

	mutex_unlock(&dev->struct_mutex);

drivers/gpu/drm/i915/i915_gem_request.c

+4 −0
Original line number Diff line number Diff line
@@ -558,6 +558,10 @@ static void i915_gem_mark_busy(const struct intel_engine_cs *engine) 
		return;



	intel_runtime_pm_get_noresume(dev_priv);



	if (NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv))

		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	dev_priv->gt.awake = true;



	intel_enable_gt_powersave(dev_priv);

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -223,6 +223,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define GEN8_CONFIG0			_MMIO(0xD00)

#define  GEN9_DEFAULT_FIXES		(1 << 3 | 1 << 2 | 1 << 1)



#define GEN8_RC6_CTX_INFO		_MMIO(0x8504)



#define GAC_ECO_BITS			_MMIO(0x14090)

#define   ECOBITS_SNB_BIT		(1<<13)

#define   ECOBITS_PPGTT_CACHE64B	(3<<8)